Over the last few years, CMOS-based (complementary metal-oxide-semiconductor) digital logic IC (integrated circuit) technologies have been devised which operate at progressively lower power supply voltages with each passing design generation. Lower supply voltages dictate lower voltage swings for the associated digital signals, which typically traverse between ground and the power supply voltage. The benefits of using lower supply voltages are lower power consumption and faster signal switching times. However, along with these advantages comes the consequence of lower noise margins. CMOS logic IC power supply voltages currently available include, for example, 3.3 V, 2.5 V, 1.8 V, and 1.5 V. Depending on the application, a mix of the various CMOS technologies may be used in any particular electronic product, necessitating the use of digital voltage level shifters to translate CMOS signals generated using one power supply voltage to signals based on a different voltage level.
With respect to transforming a low-voltage-swing digital signal to a higher-voltage-swing signal, various types of CMOS voltage level shifters have been devised over the last few years. One simple example is depicted in FIG. 1, utilizing a pair of complementary MOS FETs (Field Effect Transistors) structured as CMOS inverters. A P-FET (p-channel FET) PIN, and an N-FET (n-channel FET) NIN, form an input signal inverter 100, and another pair of complementary FETs, a P-FET POUT and an N-FET NOUT, make up an output signal inverter 110. With such a circuit, an input signal VIN with a voltage swing between ground and a low power supply voltage VDDL, is converted to an output signal VOUT, with a voltage swing between ground and a high power supply voltage VDDH. Input signal VIN is passed to input signal inverter 100, which logically inverts input signal VIN to the opposite polarity at a node 120. The signal at node 120 is then inverted once again by output signal inverter 110 to yield output signal VOUT that is of the same polarity as VIN, but possesses a higher voltage swing.
Normally, the two FETS of a CMOS inverter, such as those in FIG. 1, will work in tandem so that one FET is completely xe2x80x9cONxe2x80x9d, or conducting current between the drain and source terminals of the FET, while the other is xe2x80x9cOFFxe2x80x9d. When VIN is at a logic LOW of approximately zero volts, for example, FET NIN will be OFF, while FET PIN will be fully ON, causing node 120 to be pulled up substantially to voltage VDDH. This voltage at node 120, in turn, causes, FET POUT to turn OFF completely, while NOUT is fully ON, causing VOUT to be pulled down essentially to ground. However, in the case where VIN is at a HIGH logic state of VDDL volts, NIN is ON, while PIN is partially ON. PIN is not completely OFF in this case since the voltage at the gate of PIN is not as high as the VDDH volts imposed on the drain of PIN. Having both PIN and NIN ON results in a static current flowing from high power supply voltage VDDH to ground through input signal inverter 100. Having such static current flowing during a time when no signal transitions are occurring causes increased power consumption and unwanted heat generation by the circuit. Additionally, the phenomenon of hot electron injection, which degrades FET performance by changing the characteristics of the FET, becomes a possibility.
Other level shifters from the prior art include those employing a differential amplifier, an example of which is shown in FIG. 2. In this circuit, a bias voltage VBIAS drives the gate of an N-FET NSOURCE, to implement a constant current source 200. Connected in series with current source 200 is a left-hand branch 210. (consisting of a first load FET PLD1 and a first input FET NIN1), in parallel with a right-hand branch 220 (formed from a second load FET PLD2 and a second input FET NIN2). A reference voltage VREF is used in right-hand branch 220 as a threshold against which an input signal VIN, used by left-hand branch 210, is compared. If VIN is less than VREF, more current flows in right-hand branch 220 than in left-hand branch 210, causing node 230 to be pulled toward ground. Node 230, in turn, is input to a digital buffer 240, which converts the substantially analog signal on node 230 into a digital output signal VOUT with a voltage swing between ground and VDDH. With VIN less than VREF, output signal VOUT will be at a logic LOW, or essentially ground. Conversely, VIN being greater than VREF causes less current to flow in right-hand branch 220, thus causing node 230 to be pulled toward VDDH. Digital buffer 240 then converts the analog signal of node 230 to a digital HIGH level of VDDH at VOUT. The disadvantage of this circuit is similar to those of the level shifter of FIG. 1: static current being drawn, resulting in increased power consumption and heat generation. Additionally, the circuit of FIG. 2 requires an extremely stable reference voltage VREF. Furthermore, the like components of left-hand branch 210 and right-hand branch 220 must be closely matched in size, making the physical layout of branches 210 and 220 critical.
In addition to the aforementioned problems, neither of the level shifting circuits of FIG. 1 or FIG. 2 offers any input hysteresis. In other words, a value of input signal VIN which causes a change in output signal VOUT is the same regardless of whether input signal VIN changes from a logic LOW to HIGH, or from HIGH to LOW. Input hysteresis is valuable in noise-prone environments, and especially when using low-voltage digital logic technologies, such as those mentioned earlier, since digital signals with low-voltage swings typically allow small amounts of noise to force a signal past the threshold voltage for that logic family.
Other voltage level shifters other than those mentioned above have been developed over the years, and, by way of example, various forms of such devices can be found in U.S. Pat. Nos. 4,486,670, 4,501,978, 5,742,183, and 6,005,432.
From the foregoing, it is apparent that a need exists for a digital voltage level circuit, which converts lower-voltage-swing digital signals, to those of a higher voltage swing, while at the same time producing essentially no static current, thereby consuming less power and generating less heat. It is also desirable for such a circuit to require no reference voltage, to require no special layout considerations, and to provide some input hysteresis to protect against false logic triggering by local noise sources.
Embodiments of the invention, to be discussed in detail below, convert a digital signal with a low-voltage swing to a digital signal with a relative high-voltage swing without consuming power by way of static current. Also, no special layout considerations are required, and input hysteresis is provided to counteract the effects of noise injected into the input signal.
In one embodiment of the invention, the input signal drives a first and second input signal inverter of the voltage level shifter apparatus simultaneously. The first inverter transforms the input signal into a logically inverted form of the input signal with a high-voltage swing, while the second inverter transforms the input signal into a logically inverted signal with a relatively lower voltage swing. It is this low-voltage-swing inverter that helps provide the hysteresis exhibited by the embodiments of the invention. A third inverter is then used to invert the high-voltage-swing signal so that the proper high-voltage-swing output signal is produced. Both the high-voltage-swing signals and the low-voltage-swing signals are used to drive a feedback unit. This feedback unit, in turn, produces a feedback signal for controlling a pull-up device responsible for delivering power to the first inverter. When necessary, as will be discussed later, the pull-up device shuts off power to the first high-voltage inverter so that the voltage level shifter will draw no static current.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.